Muhammad AdnanEngineering & designIdeas engineered. Solutions delivered.

Electronics & Embedded

Report-based engineering study

VHDL Register Bank Verification

A VHDL testbench exercises an eight-bit register bank with timed writes, dual read ports and waveform inspection.

VHDLVivado Simulator 2019.1IEEE Std_logic_1164IEEE Numeric_Std
Simulator waveform with hexadecimal register values and nanosecond timing. Enlarge image
Vivado waveform showing the test patterns, read buses and four register debug outputs.
VHDL port declarations for clock, reset, register addresses, data and debug buses. Enlarge image
Original VHDL component declaration, cropped to the technical interface.
Two columns of VHDL stimulus apply 55, AA and FF before selecting register read addresses. Enlarge image
Original reset, write and read stimulus, arranged in two columns without changing its code.
VHDL Register Bank Verification — architecture diagram Enlarge image
Explanatory architecture for this project; source software evidence is shown separately.
VHDL Register Bank Verification — workflow diagram Enlarge image
Explanatory workflow for this project; source software evidence is shown separately.

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Project brief

This project documents a VHDL verification exercise for a small processor register bank. The component interface exposes two read-address inputs, one write-address input, an eight-bit data input, two eight-bit read outputs and four register debug outputs. A separate testbench instantiates that component, generates a clock and applies a timed sequence of reset, write and read operations. The written stimulus loads hexadecimal 55, AA and FF into three selected registers, disables writes, and changes the two read addresses to inspect stored values. A Vivado Simulator waveform provides direct evidence of the resulting signal activity and register contents. The report connects this practical HDL work with an educational processor discussion covering instruction fetch, decode and execution, assembly operations, addressing modes and state encoding. Its strongest portfolio evidence is the relationship between interface definition, test stimulus and visible waveform behavior. The code uses explicit timing and named port mapping, which make the intended sequence easy to follow. This is a bounded simulation exercise: the document does not provide hardware deployment, timing closure, coverage statistics or an automated assertion suite. The project therefore demonstrates digital interface modeling and manual simulation inspection rather than a fully verified processor implementation.

The engineering challenge

Exercise the storage and dual-read behavior of a processor register bank with a clear, repeatable stimulus sequence and observable internal state.

Engineering approach

  1. Declare the register-bank component using IEEE standard logic types and eight-bit data buses.
  2. Instantiate the design under test with explicit named port mapping.
  3. Generate a clock using two 50 ns waits and apply the documented reset sequence.
  4. Write three hexadecimal test patterns, disable writes and select two register pairs for reading.
  5. Inspect the simulator waveform alongside the code and register debug outputs.

Results & observations

4 × 8-bit registersRegister interface

Four eight-bit debug outputs expose the register contents; two read ports share a single write interface.

100 ns periodClock stimulus

The testbench assigns low and high clock levels for 50 ns each.

55 / AA / FFWritten test patterns

Hexadecimal data values applied to write addresses 00, 01 and 10 in the supplied stimulus.

Vivado waveformSimulation evidence

The source screenshot displays stored values 55, AA, FF and 00 on the four register debug outputs.

Features & capabilities

  • VHDL component interface
  • Named port mapping
  • Timed clock and reset
  • Sequential register writes
  • Dual read-port stimulus
  • Register waveform inspection

Software & engineering tools

VHDL, Vivado Simulator 2019.1, IEEE Std_logic_1164, IEEE Numeric_Std

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